1. Field
The disclosed configuration relates to a phase-locked loop system and to a method for operating a phase-locked loop.
2. Description of Related Art
Conventional phase-locked loops usually comprise a controlled oscillator for providing an output clock signal being controlled by some kind of control signal. A feedback signal is generated on the basis of the output clock signal and provided to a phase detector together with a reference clock signal. The phase detector provides a phase dependent signal, which for example is processed by means of a loop filter that outputs the control signal for the controlled oscillator.
During normal operation, the phase-locked loop keeps the output clock signal at a desired frequency and at a desired phase. However, during a start-up period, the phase-locked loop needs to control the controlled oscillator from a starting frequency being different from the desired output clock frequency such that both the desired frequency and the desired phase are met. It is desirable that such a start-up period is as short as possible.
To achieve a short start-up period, conventional phase-locked loops increase a gain of the control loop in order to achieve a faster change of the output frequency. However, this leads to frequency overshoots, i.e., an output frequency being higher than the desired output frequency. Hence, in such conventional approaches, the output frequency oscillates around the desired output frequency until the correct frequency and phase are reached.